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Integrated Circuit Systems, Inc.
ICS9148-53
Frequency Generator & Integrated Buffers for Mother Boards
General Description
The ICS9148-53 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro, AMD or Cyrix. Sixteen different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-53 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.
Features
Generates the following system clocks: - 3 CPU(2.5V/3.3V) up to 150MHz. - 7 PCI(3.3V) (including one free running PCICLK) - 2AGP(3.3V) @ 2 x PCI - 13 SDRAMs(3.3V) up to 150MHz - 1 REF (3.3V) @ 14.318MHz - 1 Fixed clock 3.3V @ 48MHz Skew characteristics: - CPU CPU<250ps - CPU(early) PCI : 1-4ns Supports Spread Spectrum modulation & I2C programming for Power Management, Frequency Select Efficient Power management scheme through power down CPU, PCI, AGP and CPU_STOP clocks. Uses external 14.318MHz crystal 48 pin 300mil SSOP. Read back of FS pin values from I2C

Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:12), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:3)
9148-53 Rev C 08/14/98
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9148-53
Pin Descriptions
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6 7 FS11, 2 8 10, 11, 12, 13, 47 14 15 17 PCICLK0 FS21, 2 PCICLK(1:5) VDD5 BUFFERIN CPU_STOP# SDRAM 11 18 28, 29, 31, 32, 34, 35,37,38 20 PCI_STOP#1 SDRAM 10 SDRAM (0:9) AGP_STOP#1 SDRAM9 21 19,30,36 23 24 25 MODE1, 2 48MHz 26 41, 43, 44 40 42 46 48 FS0
1, 2
PIN NAME VDD1 REF0 FS3 GND X1 X2 VDD2 PCICLK_F
TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT PWR IN IN OUT IN OUT OUT IN OUT IN OUT PWR IN IN OUT IN OUT IN OUT OUT PWR OUT PWR
DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Supply for fixed PLL, 48MHz, AGP0 Input pin for SDRAM buffers. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Supply for SDRAM (0:11), CPU Core, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Advanced Graphic Port output, powered by VDD4. Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Feedback SDRAM clock output. Supply for CPU (0:3), either 2.5V or 3.3V nominal Advanced Graphic Port output powered by VDD4. Supply for AGP (0:2)
PD#
1
SDRAM8 VDD3 SDATA SCLK AGP0
CPUCLK(0:3) SDRAM12 VDDL AGP1 VDD4
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9148-53
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Pin 20 AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# 1 1 1 0 0 1 1 1 PCI_STOP# 1 1 0 1 AGP, CPUCLK Outputs Stopped Low Running Running Running PCICLK (0:5) Running Running Stopped Low Running PCICLK_F, REF, 48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO Running Running Running Running AGP(1:2) Running Running Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
3
ICS9148-53
Functionality
VDD1, 2, 3, 4 = 3.3V5%, TA= 0 to 70C Crystal (X1, X2) = 14.31818MHz
FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CPU,SDRAM (MHZ) 133 124 150 140 105 112 115 120 100 95.25 83.3 75 75 68.5 66.8 60
PCI (MHZ) AGP (MHZ) 44.33 88.67 41.33 82.67 50 100 46.67 93.33 35 70 37.33 74.67 38.33 76.66 40 80 33.3 66.6 31.75 63.5 33.3 66.6 30 60 37.5 75 34.25 68.5 33.4 66.8 30 60
REF, IOAPIC (MHZ) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
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ICS9148-53
General I2C serial interface information
A.
Clock Generator Address (7 bits)
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with an acknoledge bit between each byte.
A(6:0) & R/W# D2(H)
B.
ACK
+ 8 bits dummy command code
ACK
+ 8 bits dummy Byte count
ACK
Then Byte 0, 1, 2, etc in sequence until STOP.
The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator Address (7 bits)
A(6:0) & R/W# D3(H)
C. D. E. F.
ACK
Byte Count Readback
ACK
Then Byte 0, 1, 2, etc. in sequence until STOP.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. The Fixed clocks 48MHz and 24MHz are not addressable in the registers for Stopping. These output are always running, except in Tristate Mode. At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled output state).
G . H.
5
ICS9148-53
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7 Description PWD 0 - 0.25% Spread Spectrum Modulation 0 1 - 0.6% Spread Spectrum Modulation Bit (2, 6:4) CPU CLKs PCI CLKs AGP CLKs 1111 133 44.33 88.67 1110 124 41.33 82.67 1101 150 50 100 1100 140 46.67 93.33 1011 105 35 70 1010 112 37.33 74.67 1001 115 38.33 76.66 Note1 1000 120 40 80 0111 100 33.33 66.60 0110 95.25 31.75 63.50 0101 83.3 33.30 66.60 0100 75 30.00 60.00 0011 75 37.50 75.00 0010 68.5 34.25 68.50 0001 66.8 33.40 66.80 0000 60 30.00 60.00 0 - Frequency is selected by hardware select, Latched Inputs 0 1 - Frequency is selected by Bit 6:4 (above) 0 - Normal 0 1 - Spread Spectrum Enabled (center spread) 0 - Running 0 1- Tristate all outputs
Bit (2, 6:4)
Bit 3 Bit 1 Bit 0
Note 1: Default at power-up will be for latched logic inputs to define frequency; Bits 2, 6:4 are default to 000
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation 6
ICS9148-53
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
B it Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 1 1 1 1 1 1 1 D e s cription (Reserved) (Reserved) (Reserved) S DRAM 12 (Act/Inact) (Reserved) C P UC LK 2 (Act/Inact) C P UC LK 1 (Act/Inact) C P UC LK 0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
B it Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 D e s cription (Reserved) P C IC LK _F (Act/Inact) (Reserved) P C IC LK 4 (Act/Inact) P C IC LK 3 (Act/Inact) P C IC LK 2 (Act/Inact) P C IC LK 1 (Act/Inact) P C IC LK 0(Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
B it Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 25 26 17 18 20 21 PWD 1 1 1 1 1 1 1 D e s cription AGP0 (Active/Inactive) (Reserved) FS0# (Reserved) SDRAM 11 (Act/Inact) (Desktop M ode O nly) SDRAM 10 (Act/Inact) (Desktop M ode O nly) SDRAM 9 (Act/Inact) SDRAM 8 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 8 7 47 2 46 2 PWD 1 1 1 1 1 Description (Reserved) FS2# FS1# PCICLK5 (Act/Inact) (Reserved) FS3# AGP1 (Act/Inact) REF0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 6: Optional Register for Possible Furture Requirements
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for futue applications.
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ICS9148-53
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-53. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-53. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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ICS9148-53
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-53. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-53 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
9
ICS9148-53
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP (0:1) clocks. for low power operation. AGP_STOP# is synchronized by the ICS9148-53. The AGP2 clock is free-running and is not affected by AGP_STOP#. All other clocks will continue to run while the AGPCLKs are disabled. The AGPCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less than 4 AGPCLKs. This function is available only with MODE pin latched low.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. AGP_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-53. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
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ICS9148-53
Shared Pin Operation Input/Output Pins
Pins 2, 7, 8, 25 and 26 on the ICS9148-53 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
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ICS9148-53
Fig. 2a
Fig. 2b
12
ICS9148-53
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0C to +70C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Transition Time Settling Time1 Clk Stabilization 1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP Fi CIN CINX Ttrans Ts TSTAB TCPU-PCI1 TCPU-PCI1 TAGP-PCI1 TAGP-PCI1 TAGP-PCI1
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; 66.8 MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; f = 66/100 MHz; CPU leads VT = 1.5 V; f = 83/75 MHz; CPU leads VT = 1.5 V; f = 66.8 MHz; AGP Leads VT = 1.5 V; f = 83.3 MHz; AGP Leads VT = 1.5 V; f = 100 MHz; AGP Leads
0.1 2.0 -100 100 14.318
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 160 mA MHz 5 45 2 2 4 4 600 700 550 pF pF ms ms ms ns ns ps ps ps
27
36
1 1
Skew1
2.4 3.8 500 600 450
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current SYMBOL IDD2.5OP TCPU-PCI1 TCPU-PCI1 TAGP-PCI1 TAGP-PCI1 TAGP-PCI1 CONDITIONS CL = 0 pF; 66.8 MHz VT = 1.5 V; f = 66/100 MHz; CPU leads VT = 1.5 V; f = 83/75 MHz; CPU leads VT = 1.5 V; f = 66.8 MHz; AGP Leads VT = 1.5 V; f = 83.3 MHz; AGP Leads VT = 1.5 V; f = 100 MHz; AGP Leads MIN TYP 10 2.4 3.8 500 600 450 MAX 20 4 4 600 700 550 UNITS mA ns ns ps ps ps
1 1
Skew1
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ICS9148-53
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2A VOL2A IOH2A IOL2A tr2A1 tf2A1 d t2A1 tsk2A1 tj1s2A1 tjabs2A1
CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.5
33
TYP 2.6 0.35 -29 37 1.75 1.1
MAX UNITS V 0.4 V -23 mA mA 2 2 55 250 150 250 ns ns % ps ps ps
45
50 50 65
-250
165
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Single Edge Displacement2 Jitter, One Sigma Jitter, Absolute
1 2
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B 1 tf2B 1 dt2B
1 1
CONDITIONS IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
TYP 2.2 0.3 -20 26 1.5 1.6
MAX UNITS V 0.4 V -16 mA mA 1.8 1.8 55 250 250 150 250 ns ns % ps ps ps ps
40
47 60 200 65
tsk2B
tjsed2B1 tj1s2B1 tjabs2B1
-250
160
Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
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ICS9148-53
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 Tr1 Tf1 Dt1 Tprop Tsk1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
41
TYP 3 0.2 -60 50 1.75 1.5
MAX UNITS V 0.4 V -40 mA mA 2 2 55 6 500 ns ns % ns ps
Duty Cycle Skew
1 1
45
Propagation Delay
50 4.2 200
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 t f1
1 1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.8 1.6
MAX UNITS V 0.4 V -40 mA mA 2 2 55 250 150 250 250 650 ns ns % ps ps ps ps ps
dt1
45
51 130 40 200
tsk1 1 tj1s1a tj1s1b tabs1a tjabs1b
1
-250 -650
135 500
Guaranteed by design, not 100% tested in production.
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ICS9148-53
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.1 1
MAX UNITS V 0.4 V -40 mA mA 2 2 55 250 3 5 6 ns ns % ps % % %
dt1 1 tsk1 1 tj1s1 tabs1a tjabs1b
45
49 130 2
-5 -6
2.5 4.5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1 1 1
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 2.6 0.3 -32 25 2 1.9
MAX UNITS V 0.4 V -22 mA mA 4 4 57 3 5 ns ns % % %
dt5
45 -5
54 1 -
tj1s5 tjabs51
Guaranteed by design, not 100% tested in production.
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ICS9148-53
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
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ICS9148-53
SYMBOL A A1 A2 B C D E e H h L N X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
48 pin SSOP Package
Ordering Information
ICS9148F-53
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
18
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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Price & Availability of ICS9148-53

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